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DS1689/DS1693
13 of 36
REGISTER A
MSB
LSB
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
UIP
DV2
DV1
DV0
RS3
RS2
RS1
RS0
Bit 7: UIP (Update In Progress). This bit is a status flag that can be monitored. When the UIP bit is 1,
the update transfer will soon occur. When UIP is 0, the update transfer will not occur for at least 244ms.
The time, calendar, and alarm information in RAM is fully available for access when the UIP bit is 0. The
UIP bit is read-only. Writing the SET bit in Register B to 1 inhibits any update transfer and clears the UIP
status bit.
Bits 6, 5, 4: DV0, DV1, DV2. These bits are defined as follows:
DV2 =
Countdown Chain
1 - resets countdown chain only if DV1 = 1
0 - countdown chain enabled
DV1 =
Oscillator Enable
0 - oscillator off
1 - oscillator on
DV0 =
Bank Select
0 - original bank
1 - extended registers
A pattern of 01X is the only combination of bits that turn the oscillator on and allow the RTC to keep
time. A pattern of 11X enables the oscillator but holds the countdown chain in reset. The next update
occurs at 500ms after a pattern of 01X is written to DV2, DV1, and DV0.
Bits 3 to 0: RS3 to RS0 (Rate Selection Bits). These four rate-selection bits select one of the 13 taps on
the 15-stage divider or disable the divider output. The tap selected can be used to generate an output
square wave (SQW pin) and/or a periodic interrupt. The user can do one of the following:
Enable the interrupt with the PIE bit;
Enable the SQW output pin with the SQWE bit;
Enable both at the same time and the same rate; or
Enable neither.
Table 2 lists the periodic interrupt rates and the square-wave frequencies that can be chosen with the RS
bits.
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